For the past several decades, the scaling of features in integrated circuits has been the driving force behind an ever-growing semiconductor industry. Scaling to smaller and smaller features enables increased densities of functional units on the limited real estate of semiconductor chips. For example, shrinking transistor size allows for the incorporation of an increased number of logic and memory devices on a microprocessor, lending to the fabrication of products with increased complexity.
Scaling has not been without consequence, however. As the dimensions of the fundamental building blocks of microelectronic circuitry are reduced and as the sheer number of fundamental building blocks fabricated in a given region is increased, the constraints on the lithographic processes used to pattern these building blocks have become overwhelming. In particular, there may be a trade-off between the smallest dimension of a feature patterned in a semiconductor stack (the critical dimension) and the spacing between such features.
Immersion lithography has been introduced as a technique to handle such issues. In immersion lithography, a liquid film is placed between a lens and a photo-resist layer in order to increase the index of refraction for the light-path from the lens to the photo-resist layer. The increased index of refraction of the liquid, versus e.g. air, enables the formation of smaller dimensions and a tighter pitch for a developed photo-resist. However, additional improvements are needed in the evolution of immersion lithography technology.